Speech+ State Machine

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This is the TSI Speech+ State Machine, as kindly provided by Ed Bernard with the caveat that it is from memory and may not be accurate.

Definitions of inputs, outputs, busses and registers

Bits are number ascending from msb to lsb. Single bits are just named

Inputs:

Start
"word" number WN1-6
Data D1-8

Outputs:

Busy
Address A1-12
Output O1-4

Busses:

Data DB1-12
Delta DLB1-2

Registers:

Word Address WAR1-12

WAR1-4 loadable from DB1-4 independently of WAR5-12 from DB5-12.
Counts upward on control signal.
Selectable onto A1-12.

Data Address DAR1-14

DAR1-4 loadable from DB1-4 independently of DAR5-12 from DB5-12 when DB5-12 loaded DB13-14 forced to zero.
Counts upward or downward.
DAR1-12 selectable onto A1-12.
DAR13-14 select successive two bit deltas from within a byte of data.

Voiced

Loadable from D1.

Stop

Loadable from D2.

Repeat R1-2

Loadable from NOT(D3-4).
Counts up.

Last Direction UP.

Output OR1-4

Forceable to 1000.
Can add or subtract 0,1,3.

State SR1-3

Loadable to any value 0-7

Pitch Period PPR1-7

Counts upwards on each clock
Forceable to 0.
PPR1 alias Reverse.
PPR0 alias Silence.
PPR0 carry used by control logic.

State Description

The initial state description didn't include phase information, as the design developed each state was divided into phase one and phase two sub states. An example is shown below. If states remain unchanged or not of consequence they are not included. The activity shown within a state is all accomplished in parallel, thus the order shown below is arbitrary.

SR=000 idle

0 → Busy
0 → OR
if Start 001 → SR

SR=001 latch "word" number, etc

1 → Busy
0 → OR
0 → DB1
WN1-6 → DB2-7
0 → DB8-12
DB1-8 → DAR1-8
DB9-12 → DAR9-12
0 → DAR13-14
DAR1-12 → A1-12
010 → SR

SR=010 latch WAR msb

1 → Busy
0 → OR
D5-7 → DB9-12
DB9-12 → WAR1-4
DAR+1 → DAR
DAR1-12 → A1-12
if Start 001 → SR
else 011->SR

SR=011 latch WAR lsb

1 → Busy
0 → OR
D1-8 → DB1-8
DB1-8 → WAR5-12
WAR1-12 → A1-12
if Start 001 → SR
else 100->SR

SR=100 latch DAR msb, etc.

1 → Busy
0 → OR
D5-7 → DB9-12
DB9-12 → DAR1-4
D1 → Voiced
D2 → Stop
NOT(D3-4) → Repeat1-2
WAR+1 → WAR
WAR1-12 → A1-12
if Start 001 → SR
else 101->SR

SR=101 latch DAR lsb, get ready for new pitch period

1 → Busy
0 → OR
D1-8 → DB1-8
DB1-8 → DAR5-12
0 → DAR13-14
1 → UP
0 → PPR1-7
WAR+1 → WAR
DAR1-12 → A1-12
if Start 001 → SR
else 110->SR

SR=110 play Repeat+1 number of pitch periods

This is the most complicated state as it really has 128 sub states, defined by PPR1-7, with each sub state having two phases. It is not completed here.

ROM/S14001A phasing

Up until now very little had been assumed about the implementation of the chip. But here it becomes two phase logic with state saved for each phase. It is heading towards dynamic logic.

Very early in the design the ROM was selected. The ROM chosen had a simple clocking scheme which only required a simple single clock. Previous versions of ROM had more complicated clocking with precharge and read signals. For the ROM chosen, the clock rose then fell. The address lines were required to be stable a small setup and hold time when it fell. Data was available shortly after the clock fell. The clock was termed address read.

For the S14001A the addresses were output at the beginning of phase two and phase two was output as "Address Read". The addresses remained stable until the next phase two, thus ensuring setup and hold times were met.

Data from the ROM was available very early in phase one and remained stable until the next falling address read, i.e. late in phase two. Almost all logic was performed during phase one.

So the state descriptions are split into two phases and SR=100 and 101 are rewritten as examples. All registers have state saved for two phases as indicated by a following P1 or P2. All registers transfer P1 to P2 during phase two so those implied transfers are omitted below.

SR=100P1 latch DAR msb, etc.

1 → Busy
0 → OR
D5-7 → DB9-12P1
DB9-12 → DAR1-4P1
D1 → VoicedP1
D2 → StopP1
D3-4 → Repeat1-2P1
WARP2+1 → WARP1
if Start 001 → SRP1
else 101->SRP1

SR=004P2

WAR1-12P2 → A1-12

SR=005P1 latch DAR lsb, get ready for new pitch period

1 → Busy
0 → OR
D1-8 → DB1-8
DB1-8 → DAR5-12P1
0 → DAR13-14P1
1 → UPP1
0 → PPR1-7P1
WARP2+1 → WARP1, ready to access next control word
if Start 001 → SRP1
else 110->SRP1

SR=005P2

DAR1-12P2 → A1-12, ready to access first delta data for pitch period

State change coding for SR110
SR=110P1 play pitch period, in part

1->Busy
if Start 001 → SRP1
else if PRR0CarryP1
    RepeatP1 = RepeatP2+1
    if StopP2 and RepeatP2 = 11
        000 → SRP1, enter idle state
    else if RepeatP2 = 11
        100 → SRP1, start new control word
    else
        110 → SRP1, a new pitch period is starting
    else
        110 → SRP1, continue playing pitch period

SR=110P2

if SRP2 = 100 WAR1-12P2 → A1-12, get correct address out for next P1
else DAR1-12P2 → A1-12

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